1 HIP4020 half amp full bridge power driver for small 3v, 5v and 12v dc motors description in the functional block diagram of the HIP4020, the four switches and a load are arranged in an h-con?uration so that the drive volt- age from terminals outa and outb can be cross-switched to change the direction of current ?w in the load. this is commonly known as 4-quadrant load control. as shown in the block diagram, switches q1 and q4 are conducting or in an on state when current ?ws from v dd through q1 to the load, and then through q4 to termi- nal v ssb ; where load terminal outa is at a positive potential with respect to outb. switches q1 and q4 are operated synchronously by the control logic. the control logic switches q3 and q2 to an open or off state when q1 and q4 are switched on. to reverse the cur- rent ?w in the load, the switch states are reversed where q1 and q4 are off while q2 and q3 are on. consequently, current then ?ws from v dd through q3, through the load, and through q2 to terminal v ssa , and load terminal outb is then at a positive potential with respect to outa. terminals ena and enb are enable inputs for the logic a and b input controls. the ilf output is an over-current limit fault flag out- put and indicates a fault condition for either output a or b or both. the v dd and v ss are the power supply reference terminals for the a and b control logic inputs and ilf output. while the v dd positive power supply terminal is internally connected to each bridge driver, the v ssa and v ssb power supply terminals are separate and independent from v ss and may be more negative than the v ss ground reference termi- nal. the use of level shifters in the gate drive circuitry to the nmos (low-side) output stages allows controlled level shifting of the output drive relative to ground. ordering information part number temp. range ( o c) package pkg. no. HIP4020ib -40 to 85 20 ld soic m20.3 features two independent controlled complementary mos power output half h-drivers (full-bridge) for nominal 3v to 12v power supply operation split voltage power supply option for output drivers load switching capabilities to 0.5a single supply range +2.5v to +15v low standby current cmos/ttl compatible input logic over-temperature shutdown protection over-current limit protection over-current fault flag output direction, braking and pwm control applications dc motor driver relay and solenoid drivers stepper motor controller air core gauge instrument driver speedometer displays tachometer displays remote power switch battery operated switch circuits logic and microcontroller operated switch june 1997 pinout HIP4020 soic top view block diagram 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 nc ilf b2 enb b1 v ss a1 ena a2 nc nc nc outb v ssb v dd v ssa outa nc v dd nc v ssb v dd outb load outa b1 b2 enb a1 a2 ena ilf v ss v ssa q1 q3 q2 q4 control logic b control logic a i sense t sense i sense i sense i sense over temp. and current limit, level shift, drive control file number 3976.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999
2 HIP4020 absolute maximum ratings thermal information supply voltage; v dd to v ss or v ssa or v ssb . . . . . . . . . . . . . . +15v neg. output supply voltage, (v ssa , v ssb ). . . . . . . . . . . . . (note 1) dc logic input voltage (each input) . . . (v ss -0.5v) to (v dd +0.5v) dc logic input current (each input) . . . . . . . . . . . . . . . . . . . . . 15ma ilf fault output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma output load current, (self limiting, see elec. spec.) . . . . . i o(limit) operating conditions t a = 25 o c typical operating supply voltage range, v dd . . . . . . . . +3 to +12v low voltage logic retention, min. v dd . . . . . . . . . . . . . . . . . . . +2v idle supply current; no load, v dd = +5v . . . . . . . . . . . . . . . 0.8ma typical p+n channel r ds(on) , v dd = +5v, 0.5a load . . . . . . . . . 2 ? thermal resistance (typical, note 1) ja plastic soic package . . . . . . . . . . . . . . . . . . . . . . . . . . 105 o c/w maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (lead tips only) caution: stresses above those listed in ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations t a = 25 o c, v dd = +5v, v ssa = v ssb = v ss = 0v, unless otherwise speci?d parameter symbol test conditions min typ max units input leakage current i leak v dd = +15v - - 25 na low level input voltage v il v ss - 0.8 v high level input voltage v ih 2 - v dd v ilf output low, sink current i oh v out = 0.4v, v dd = +12v 15 - - ma ilf output high, source current i ol v out = 11.6v, v dd = +12v - - -15 ma input capacitance c in - 2-pf p-channel r ds(on) , low supply voltage r ds(on) v dd = +3v, i source = 250ma - 1.6 2.1 ? n-channel r ds(on) , low supply voltage r ds(on) v dd = +3v, i sink = 250ma - 1 1.5 ? p-channel r ds(on) , high supply voltage r ds(on) v dd = +12v, i source = 400ma - 0.6 1.2 ? n-channel r ds(on) , high supply voltage r ds(on) v dd = +12v, i sink = 400ma - 0.5 1.1 ? outa, outb source current limiting i o(limit) v dd = +6v, v ss = 0v, v ssa = v ss b = -6v 480 625 1500 ma outa, outb sink current limiting -i o(limit) v dd = +6v, v ss = 0v, v ssa = v ss b = -6v 480 800 1500 ma idle supply current; no load i dd - 0.8 1.5 ma outa, outb voltage high v oh i source = 450ma 4.2 4.5 - v outa, outb voltage low v ol i sink = 450ma - 0.4 0.6 v outa, outb voltage high v oh v dd = +3v, i source = 250ma 2.415 2.6 - v outa, outb voltage low v ol v dd = +3v, i sink = 250ma - 0.25 0.375 v outa, outb source current limiting i o(limit) v dd = +12v 480 625 1500 ma outa, outb sink current limiting -i o(limit) v dd = +12v 480 800 1500 ma outa, outb source current limiting i o(limit) v dd = +3v 480 625 1500 ma outa, outb sink current limiting -i o(limit) v dd = +3v 480 800 1500 ma thermal shutdown t sd - 145 - o c
3 HIP4020 response time: v en to v out i o = 0.5a (note 2) turn-on: prop delay t plh - 2.5 - s rise time t r -4- s turn-off: prop delay t phl - 0.1 - s fall time t f - 0.1 - s notes: 1. v ss is the required common ground reference for the logic input switching. the load currents may be switched positive and negative in reference to the v ss common ground by using a split supply for v dd (positive) to v ssa and v ssb (negative). for an uneven split in the supply voltage, the maximum negative output supply voltage for v ssa and v ssb is limited by the maximum v dd to v ssa or v ssb ratings. since the v dd pins are internally tied together, the voltage on each v dd pins must be equal and common. 2. refer to the truth table and the v en to v out switching waveforms. current, i o refers to i outa or i outb as the output load current. note that ena controls outa and enb controls outb. each half h-switch has independent control from the respective a1, a2, ena or b1, b2, enb inputs. refer to the terminal information table for external pin connections to establish mode control switching. figur e 1 shows a typical application circuit used to control a dc motor. pin descriptions pin number symbol description 12, 19 v dd positive power supply pins; internally common and externally connect to the same positive supply (v+). 15 v ssa negative power supply pin; negative or ground return for switch driver a; externally connect to the supply (v-). 16 v ssb negative power supply pin; negative or ground return for switch driver b; externally connect to the supply (v-). 6v ss common ground pin for the input logic control circuits. may be used as a common ground with v ssa and v ssb. 8, 5 a1, b1 input pins used to control the direction of output load current to/from outa and outb, respectively. when connected, a1 and b1 can be controlled from the same logic signal to change the directional rotation of a motor. 9, 3 a2, b2 input pins used to force a low state on outa and outb, respectively. when connected, a2 and b2 can be controlled from the same logic signal to activate dynamic braking of a motor. 7, 4 ena, enb input pins used to enable switch driver a and switch driver b, respectively. when low, the respec- tive output is in a high impedance (z) off-state. since each switch driver is independently controlled, outa and outb may be a separately pwm controlled as half h-switch drivers. 14, 17 outa, outb respectively, switch driver a and switch driver b output pins. 2 ilf current limiting fault output flag pin; when in a high logic state, signifies that switch driver a or b or both are in a current limiting fault mode. electrical speci?ations t a = 25 o c, v dd = +5v, v ssa = v ssb = v ss = 0v, unless otherwise speci?d (continued) parameter symbol test conditions min typ max units
4 HIP4020 figure 1. typical motor control application circuit showing directional and braking control b1 b2 enb a1 a2 ena v dd v ss v ssb v ssa v+ outa outb brake on off direction enable (logic ground) load ilf q1 q3 q2 q4 d1 d3 d4 d2 control logic a v- level shifter and oc/ot limiter level shifter and oc/ot limiter over-temp limit control logic b truth table switch driver a switch driver b inputs output inputs output a1 a2 ena outa b1 b2 enb outb hl h oh ll h oh ll h ol hl h ol hh h ol lh h ol lh h ol hh h ol xx l z xx l z l = low logic level; h = high logic level z = high impedance (off state) oh = output high (sourcing current to the output terminal) ol = output low (sinking current from the output terminal) x = don? care switching waveforms t plh 50% 50% v en v out t phl 50% 50% v en v out t r t f 10% 90% 10% 90% figure 2.
5 HIP4020 application the HIP4020 is designed to detect load current feedback from sampling resistors of low value in the source connections of the output drivers to v dd , v ssa and v ssb (see figure 1). when the sink or source current at outa or outb exceeds the preset oc (over-current) limiting value of 550ma typical, the current is held at the limiting value. if the ot (over-temperature) shut- down protection limit is exceeded, temperature sensing bimos circuits limit the junction temperature to 150 o c typical. the circuit of figure 1 shows the full h-switch in a small motor- drive application. the left (a) and right (b) h-switch s are con- trolled from the a and b inputs via the a and b control logic to the mos output transistors q1, q2, q3 and q4. the circuit is intended to safely start, stop, and control rotational direction for a motor requiring no more than 0.5a of supply cur- rent. the stop function includes a dynamic braking feature. with the enable inputs low, the mos transistors q1 and q3 are off; which cuts-off supply current to outa and outb. with the brake terminal low and enable inputs high, either q1 and q4 or q3 and q2 will be driven into conduction by the direction input control terminal. the mos output transistor pair chosen for conduction is determined by the logic level applied to the direction control; resulting in either clockwise (cw) or counter-clockwise (ccw) shaft rotation. when the brake terminal is switched high (while holding the enable input high), the gates of both q2 and q4 are driven high. current ?wing through q2 (from the motor ter- minal outa) at the moment of dynamic braking will con- tinue to ?w through q2 to the v ssa and v ssb external connection, and then continue through diode d4 to the motor terminal outb. as such, the resistance of the motor winding (and the series-connected path) dissipates the kinetic energy stored in the system. reversing rotation, current ?wing through q4 (from the motor terminal outb), at the moment of dynamic braking, would continue to ?w through q4 to the v ssb and v ssa tie, and then continue through diode d2 to the motor terminal outa, to dissipate the stored kinetic energy as previously described. where v dd to v ss are the power supply reference terminals for the control logic, the lowest practical supply voltage for proper logic control should be no less than 2.0v. the v ssa and v ssb terminals are separate and independent from v ss and may be more negative than the v ss ground reference terminal. however, the maximum supply level from v dd to v ssa or v ssb must not be greater than the absolute maxi- mum supply voltage rating. terminals a1, b1, a2, b2, ena and enb are internally con- nected to protection circuits intended to guard the cmos gate-oxides against damage due to electrostatic discharge. (see figure 3) inputs ena, enb, a1, b1 a2 and b2 have cd74hct4000 logic interface protection and level con- verters for ttl or cmos input logic. these inputs are designed to typically provide esd protection up to 2kv. how- ever, these devices are sensitive to electrostatic discharge. proper i.c. handling procedures should be followed. figure 3. logic input esd interface protection input level conv. v dd figure 4. equivalent control logic a and b shown driving the outa and outb output drivers a1 a2 ena (dir) (brake) (enable) ot and oc protect n-dr limit p-dr limit q2 d2 q1 d1 v dd v ssa outa b1 b2 enb (dir) (brake) (enable) ot and oc protect n-dr limit p-dr limit q4 d4 q3 d3 v dd v ssb outb
6 HIP4020 typical performance curves figure 5. typical characteristic of the p-mosfet output driver drain current vs drain-to-source voltage, t ambient = 25 o c figure 6. typical characteristic of the n-mosfet output driver drain current vs drain-to-source voltage, t ambient = 25 o c figure 7. typical characteristic of the p and n output driver short circuit current vs supply voltage, t ambient = 25 o c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 drain-to-source voltage (v) v dd = 3v v dd = 5v v dd = 12v p-channel drain current (ma) typical current limiting 1 ? 0.5 ? 2 ? 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 1 ? 0.5 ? 2 ? drain-to-source voltage (v) n-channel drain current (ma) v dd = 3v v dd = 5v v dd = 12v typical current limiting 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 short circuit current (ma) v dd supply voltage (v) n-channel p-channel
7 HIP4020 figure 8. typical characteristic of saturation voltage vs output current using a +5v supply, t ambient = 25 o c figure 9. typical characteristic of saturation voltage vs output current using a 3v split supply, output reference equal logic ground, t ambient = 25 o c figure 10. typical characteristic of saturation voltage vs output current using a 6v split supply, output reference equal logic ground, t ambient = 25 o c typical performance curves (continued) output current, i o (a) saturation voltage, v dd - v out (v) high low v dd = +5v v ss = v ssa = v ssb = gnd 0 100 200 300 400 500 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 HIP4020 split 5v common ground v sat (p) v sat (n) v sat vs load current output current, i o (a) saturation voltage, v dd - v out (v) high low v dd = +3v v ss = gnd v ssa = v ssb = -3v 0 100 200 300 400 500 600 700 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 HIP4020 split 3v v sat (p) v sat (n) v sat vs load current output current, i o (a) saturation voltage, v dd - v out (v) v dd = +6v v ss = gnd v ssa = v ssb = -6v 0 100 200 300 400 500 600 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 HIP4020 split 6v v sat (p) v sat (n) v sat vs load current high low
8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 HIP4020 notes: 1. symbols are de?ed in the ?o series symbol list?in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 0 12/93 small outline plastic packages (soic)
|
